1. Field of the Invention
The present invention relates to a semiconductor storage device and a method of fabricating thereof, and more particularly to a semiconductor storage device having a memory capacitor such as a DRAM, and a method of fabricating thereof.
2. Description of the Related Art
In recent years, semiconductor devices have been getting more and more microminiaturized and highly integrated. With this trend, resolution technique in the photolithography has already advanced to almost its exposure limit. Concerning mask alignment technique in the photolithography, however, much progress has not been made yet. Under such circumstances, indicated below are prior arts that disclose a semiconductor storage device which is designed to embody the high integration and the microminiaturization by using a microscopic contact hole, and a method of fabricating thereof.
(1) JP-A-2-133924
A silicon oxide film, a PSG film and a silicon nitride film, which have been formed one by one on a silicon substrate, are etched so as to form a contact hole. Then, a CVD silicon oxide film is deposited on the silicon nitride film so that the contact hole is buried. After that, an anisotropic etching of the CVD silicon oxide film is performed with the silicon nitride film as a stopper, thus forming a side wall on the sides of the contact hole and silicon nitride film. This makes it possible not only to decrease the diameter of the contact hole but also to eliminate protuberances on the side wall, thus allowing planarization of the surface to be accomplished.
(2) JP-A-4-130722
A first interlayer film, a second interlayer film and a silicon nitride film, which have been formed one by one on a silicon substrate, are etched so as to form a taper-shaped bit contact hole. Then, a CVD oxide film is deposited inside the bit contact hole and on the silicon nitride film. After that, the CVD oxide film on the silicon nitride film is etched with the silicon nitride film as a stopper, thereby forming a side wall which comprises the CVD oxide film inside the bit contact hole. At this time, the silicon nitride film is also etched. This makes it possible not only to decrease the diameter of the bit contact hole but also to prevent a reverse taper of the bit contact hole even if a film of no good step coverage is employed.
(3) JP-A-64-77170
A gate oxide film, a gate electrode, an interlayer insulating film and a high melting point metal silicide film are formed one by one on a p-type silicon substrate. The gate oxide film, the interlayer insulating film and the high melting point metal silicide film are etched so as to form a contact hole that is in contact with the gate electrode. Then, the side of the gate electrode exposed from the contact hole and the surface of the p-type silicon substrate exposed from the contact hole are oxidized so as to form an oxide film. A CVD oxide film is deposited on the high melting point metal silicide film so that the contact hole is buried. After that, an anisotropic etching of the CVD oxide film is performed by the time the surface of the high melting point metal silicide film is exposed, thus leaving the CVD oxide film only on the side wall of the contact hole. After that, an interconnection is formed on the high melting point metal silicide film so that the contact hole is buried. This makes it possible to form the interconnection self-consistently without developing a short-circuit with the gate electrode, and at the same time the high melting point metal silicide film, which lies under the interconnection, enables the reliability to be enhanced.
However, in trying to make the DRAM microminiaturized and highly integrated, the element the design rule of which is the severest is a storage contact hole for connecting a lower electrode (a storage node electrode) of the memory capacitor with a source (or a drain) of an access transistor. In particular, when forming a DRAM of COB (Capacitor Over Bitline) structure in which a bit line is formed under the lower electrode, it is required to form the storage contact hole in such a manner that there occur no short-circuits between the bit line and the lower electrode as well as between a word line (a gate electrode) and the lower electrode.